Siemens / Mentor Graphics Full Suite

Sada Siemens (dříve Mentor Graphics) Full Suite nabízí celou řadu nástrojů a je dostupná přes projekt Europractice.

Celý seznam dostupných nástrojů: https://www.europractice.stfc.ac.uk/tools/siemens_details.html

Detaily o jednotlivých nástrojích: https://eda.sw.siemens.com/en-US/resources (shrnutí je typicky v kategorii „fact sheet“)

Stručné shrnutí jednotlivých položek je níže - anglické texty jsou převzaty ze stránek výrobce.

Pokud máte zkušenosti a/nebo další informace o jednotlivých nástrojích - doplňte je. Díky

Většina nástrojů je k dispozici na adrese, kterou lze najít na stránkách https://courses.fit.cvut.cz/NI-SIM/labs/install.html, jinak je třeba kontaktovat Martina Novotného.

Pro celou sadu měla být stejná síťová licence:

• Do systémových proměnných prostředí OS je třeba přidat cestu k licenci…
  • Název proměnné: LM_LICENSE_FILE
  • Hodnota proměnné: 1717@moon.fit.cvut.cz
• … a být na síti ČVUT (nebo přes VPN).

• ? (amsv)
• Calibre
  • The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today's markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.
• Catapult
  • Catapult High-Level Synthesis solutions deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization to elevate your designs.
• Catapult Coverage
  • Catapult Coverage provides HLS-aware code coverage, including statement, branch, condition, FEC and array access coverage, for C++/SystemC HLS designs. It also provides SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses within C++/SystemC test benches.
• Catapult Formal? (formalpro)
  • Formally find ambiguities and undesirable design issues, and user constraint problems early in the HLS design and verification process. CFormal Apps target specific logic areas with specific preset tests and property checks. CFormal Tools enable verification and coverage closure flow at C-level.
• HDL Designer
  • HDL Designer se měl používat v předmětu NI-SIM jako vývojové prostředí. Verze 2020.4 se ale neosvědčila - při spuštění simulace (pomocí Questy) se poměrně často stávalo, že si HDL Designer nevšiml, že se některý soubor změnil a neprovedl opakovanou kompilaci (bylo nutno smazat adresář work v projektu, aby se soubory zkompilovaly znovu).
  • HDL Designer combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases productivity of individual engineers and teams (local or remote) and enables a repeatable and predictable design process.
• HyperLynx
  • HyperLynx combines ease of use with automated workflows to make high-speed design analysis accessible to mainstream system designers. This allows problems to be identified and resolved early in the design cycle. HyperLynx works with multiple PCB tools and is an ideal addition to any PCB design flow.
• Leonardo Spectrum
• Oasys
  • Oasys-RTL addresses the need for higher capacity, faster runtimes, improved QoR, and physical awareness by optimizing at a higher level of abstraction and using integrated floorplanning and placement capabilities.
• PADS Professional
  • With this Hybrid-SaaS solution you will have access to cloud collaboration and version management, part selection, library creation, component sourcing data and even more tools that enable a complete PCB Design flow.
• Precision RTL Synthesis
  • Precision RTL Plus, offers best-in-class quality of results with a vendor-independent FPGA synthesis solution, and adds DO-254 certification utilities for mil-aero applications, on-chip debug and validation and resource optimization for DSPs and RAMs.
• Questa
  • Questa se používá v předmětu NI-SIM jako simulátor VHDL/(System)Verilog. Questa je vyšší licence ModelSim-u a umožňuje např. i kontrolu pokrytí.
  • Verze 2023.4 je (nejspíše) jenom pro Linux - ostatní jsou i pro Windows.
  • Link ke stažení, návod na instalaci, licenci a základní použití: https://courses.fit.cvut.cz/NI-SIM/labs/install.html
  • The Questa advanced simulator is the core simulation and debug engine of the Questa verification solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.
• ReqTracer
  • Determining if design requirements are met implies you can track them from specification through RTL description and on to verification results—a best practice for any requirements-based design flow. ReqTracer lets you easily implement and track a requirements-driven project development process.
• SLEC System
  • Formally verify the correctness of hand-written RTL vs High-Level models using Sequential Logic Equivalence Checking. Even with differences in language, timing, and interfaces, SLEC-System verifies manual RTL with Catapult Formal proving C++ vs Catapult generated RTL.
• Tanner Tools
  • Tanner Designer is an analog verification management tool that tracks all simulations for a project. The tool displays simulation results in a convenient dashboard allowing the team to quickly see which blocks pass or fail specifications and to monitor verification progress. The tool is fully integrated with S-Edit, Analog FastSPICE (AFS), T-Spice, Eldo, and the Tanner Waveform Viewer.
• Tessent
  • The Tessent silicon lifecycle solutions provide IP and applications that detect, mitigate and eliminate risks throughout the IC lifecycle, from the design-for-test phase through continuous IC monitoring. Tessent helps customers address their debug, manufacturing test, yield, functional safety, IC security, and optimization requirements for today's most complex SoCs.
• Vista
  • The Vista Flow consists of the steps typically used by SoC architects, hardware engineers, and software engineers to create TLM Models, assemble and configure the system, simulate, verify and debug, analyze and optimize performance, and power and integrate with the software.
• (Questa) Visualizer Debug Environment
  • Questa Visualizer Debug Environment is SystemVerilog class-based and UVM-aware to speed up overall debug time, even on today's most complex SoCs and FPGAs.
• Xpedition (AMS - automated PCB parasitic extraction)
  • Siemens has integrated Xpedition AMS with HyperLynx Advanced 3D Electromagnetic Solvers to provide a unique and powerful solution for calculating layout parasitics and analyzing their effect on a circuit’s function - before committing valuable resources to prototype manufacture and test.